The trend in modern central processing units (CPUs) and microprocessors is to reduce the power supply operating voltage in order to reduce power consumption and increase the chip density. The power supply reduction may impact other performance considerations as well. Due to the design considerations, memory devices, such as dynamic random access memories (DRAMs), may operate at a different supply voltage than the CPU. Some devices also may be required to use more than one power supply voltage so they can signal a CPU related device at one voltage and other devices at another voltage. The signals are generally generated by one circuit and are received by another circuit.
One such configuration occurs with modern microprocessors that operate with a nominal power supply voltages of about 2.5V, 1.8V, or lower, while other circuits in the computer operate with a power supply voltage of about 3.3V. To facilitate communication between devices operating at different voltages, an input buffer/level shifter circuit is used.
Referring to FIG. 1, a circuit diagram illustrates a conventional level shifter 10. The level shifter 10 generates an output signal LSOUT in response to an input signal TTLIN. The level shifter 10 has a stage 12 and a stage 14. The stage 12 is a CMOS inverter powered by the I/O power supply VCCIO. The stage 14 is a CMOS inverter powered by the core supply VPWR. The signal TTLIN swings between ground and VCCIO. The stage 12 inverts the signal TTLIN and presents the inverted signal to the stage 14. The swing of the output of 12 is between ground and VCCIO. The stage 14 inverts the signal received from the stage 12 and presents the signal LSOUT at an output. The signal LSOUT swings between ground and VPWR.
Referring to FIG. 2, a circuit diagram illustrates another conventional level shifter 10'. The circuit 10' has two stages 12' and 14'. The stage 12' consists of a differential amplifier 18 and a voltage reference generator (VRG) 16. The VRG 16 is connected to the positive input 20 of the differential amplifier 18. The VRG sets the trip point for the stage 12'. The input signal TTLIN is presented at the negative input 22. The differential amplifier 18 presents a signal indicative of the input level with respect to the VRG level. The stage 14' is a CMOS inverter powered by the core supply VPWR. The stage 14' inverts the signal received from the differential amplifier 18 and generates the signal LSOUT that swings between ground and VPWR.
With the increasing speeds and ever shrinking area that modern chips must work with, an input buffer/level shifter that operates faster, requires less space than the conventional designs, and uses no standby current for low power is desirable. The VRG 16 uses a current source, and requires standby current.